As examples of semiconductor integrated circuits in which the timing operation is capable of being adjusted by adjusting a delay in a semiconductor device after its fabrication, thereby enabling a device that has failed to be utilized as a pass device, refer to the descriptions rendered in Patent Documents 1, 2 and Non-Patent Document 1, etc., by way of example. A digital system (clock adjustment method) disclosed in Patent Document 1 includes a semiconductor integrated circuit device 1, a digital test signal generation apparatus 8, a digital signal observation apparatus 7 for operating upon obtaining a signal indicative of the internal status of a digital system, and an adjustment apparatus 6, as illustrated in FIG. 7. FIG. 8 (FIG. 13 in Patent Document 1) is a diagram useful in describing the operation of FIG. 7.
Following fabrication of the semiconductor integrated circuit, the digital test signal generation apparatus 8 generates a signal (step S2 in FIG. 8), the condition of propagation of the signal in the semiconductor integrated circuit device 1 is measured (step S3 in FIG. 8) utilizing the digital signal observation apparatus 7 which receives one or mode signals each indicative of an internal state of a digital system and one or more digital output signals. If there is an error in operation, then the adjustment apparatus 6 performs an adjustment so as to accommodate for variations in the semiconductor integrated circuit device using a value measured from the propagation condition (step S6 in FIG. 8). As a result of this adjustment operation, a delay is inserted for the purpose of accommodating for variations in a clock line that drives the semiconductor integrated circuit, thereby causing the variations to be absorbed. This enables a semiconductor integrated circuit decided once to be a fail device to be used as a pass device.
After the adjustment apparatus 6 completes the adjustment operation, the series of operations (steps S2 to S7 in FIG. 8), which includes again generating the signal from the digital test signal generation apparatus 8, applying this signal to the semiconductor integrated circuit device 1 and performing the adjustment by the adjustment apparatus 6 utilizing the result of observing the outputs of the semiconductor integrated circuit device by the digital signal observation apparatus 7, is repeatedly executed until a pass ratio that utilizes the result of observation by the digital signal observation apparatus 7 falls below a fixed value. That is, internal and external observation of the state of propagation in the semiconductor integrated circuit device 1 and multiple measurements utilizing the results of observation are required.
Patent Document 2 discloses a system LSI shown in FIG. 9. As shown in FIG. 9, provided on a clock supply path to a specific block 20 such as a ROM is a clock delay circuit 30, which is composed of a plurality of cascade-connected delay elements 31a to 31c and a selector 32, for selectively outputting a delay clock signal DCK in accordance with a delay control signal DCN. When a product device is tested, the operation of the specific block 20 is tested by applying the delay control signal DCN from a delay adjustment terminal 51 via a selector 43, the value of the delay control signal DCN for which normal operation is obtained is examined, and the value of a suitable delay control signal obtained by a product test is stored in a delay setting circuit 40, which is constituted by a fuse circuit or PROM. At the time of a normal operation, the content stored in the delay setting circuit 40 is applied to the clock delay circuit 30 via the selector 43. That is, the value of the delay control signal for which normal operation is obtained following fabrication of the semiconductor integrated circuit is found by a test, the value is applied to the clock delay circuit 30 and a fail semiconductor integrated circuit can be utilized as a pass semiconductor integrated circuit. In a manner similar to that of Patent Document 1 described above, this arrangement also requires that the value of a delay signal be found by testing.    [Patent Document 1]
JP Patent No. 3893147    [Patent Document 2]
Japanese Patent Kokai Publication No. JP2006-012046A
[Non-Patent Document 1]
E. Takahashi, et al., Post Fabrication Clock Timing Adjustment for Digital LSIs with Genetic Algorithms, IEEE Journal of Solid State Circuits, Vol. 39, Issue 4, April 2004, 643-650.